/*
 * AVR DDS 2tone generator
 *
 * Created: 2013/05/21 15:17:49
 * Author: www.henteko.org
 */ 

#include <avr/io.h>
#include <util/delay.h>
#include <avr/interrupt.h>
#include <stdio.h>

#define cbi(addr,bit)     addr &= ~(1<<bit)
#define sbi(addr,bit)     addr |=  (1<<bit)

#define SF 		100000 		// Sampling Frequency 100KHz
#define ACCU	65536		// Accumulator
#define MAX		3000		// max frequency
#define MIN		500			// minimum frequency
#define DEF_LOW		700		// default upside frequency
#define DEF_HIGH	2100	// default downside frequency
#define FREQ_STEP	100		// frequency incremental step

unsigned int delta1, delta2;		// incremental value
unsigned int phe1, phe2;			// phase
unsigned int pos1, pos2;			// wave table position

const unsigned char sinewave[] =	// sine wave table 256 values
{
0x80,0x83,0x86,0x89,0x8c,0x8f,0x92,0x95,0x98,0x9c,0x9f,0xa2,0xa5,0xa8,0xab,0xae,
0xb0,0xb3,0xb6,0xb9,0xbc,0xbf,0xc1,0xc4,0xc7,0xc9,0xcc,0xce,0xd1,0xd3,0xd5,0xd8,
0xda,0xdc,0xde,0xe0,0xe2,0xe4,0xe6,0xe8,0xea,0xec,0xed,0xef,0xf0,0xf2,0xf3,0xf5,
0xf6,0xf7,0xf8,0xf9,0xfa,0xfb,0xfc,0xfc,0xfd,0xfe,0xfe,0xff,0xff,0xff,0xff,0xff,
0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0xfe,0xfd,0xfc,0xfc,0xfb,0xfa,0xf9,0xf8,0xf7,
0xf6,0xf5,0xf3,0xf2,0xf0,0xef,0xed,0xec,0xea,0xe8,0xe6,0xe4,0xe2,0xe0,0xde,0xdc,
0xda,0xd8,0xd5,0xd3,0xd1,0xce,0xcc,0xc9,0xc7,0xc4,0xc1,0xbf,0xbc,0xb9,0xb6,0xb3,
0xb0,0xae,0xab,0xa8,0xa5,0xa2,0x9f,0x9c,0x98,0x95,0x92,0x8f,0x8c,0x89,0x86,0x83,
0x80,0x7c,0x79,0x76,0x73,0x70,0x6d,0x6a,0x67,0x63,0x60,0x5d,0x5a,0x57,0x54,0x51,
0x4f,0x4c,0x49,0x46,0x43,0x40,0x3e,0x3b,0x38,0x36,0x33,0x31,0x2e,0x2c,0x2a,0x27,
0x25,0x23,0x21,0x1f,0x1d,0x1b,0x19,0x17,0x15,0x13,0x12,0x10,0x0f,0x0d,0x0c,0x0a,
0x09,0x08,0x07,0x06,0x05,0x04,0x03,0x03,0x02,0x01,0x01,0x00,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x02,0x03,0x03,0x04,0x05,0x06,0x07,0x08,
0x09,0x0a,0x0c,0x0d,0x0f,0x10,0x12,0x13,0x15,0x17,0x19,0x1b,0x1d,0x1f,0x21,0x23,
0x25,0x27,0x2a,0x2c,0x2e,0x31,0x33,0x36,0x38,0x3b,0x3e,0x40,0x43,0x46,0x49,0x4c,
0x4f,0x51,0x54,0x57,0x5a,0x5d,0x60,0x63,0x67,0x6a,0x6d,0x70,0x73,0x76,0x79,0x7c,
};

//----------------------------------------------------------------
// millisecond order delay
// ---------------------------------------------------------------
void delay_ms(unsigned int t)
{
	while(t--) {
		_delay_ms(1);
	}
}

//----------------------------------------------------------------
// Timer1 Compare match interrupt (DDS output)
// ---------------------------------------------------------------
ISR(TIMER0_COMPA_vect)
{
	phe1 += delta1;		// phase accumulator
	pos1 = phe1 >> 8;	// division 256
	phe2 += delta2;		// phase accumulator
	pos2 = phe2 >> 8;	// division 256

	if(delta1 == delta2)
		PORTA = sinewave[pos1];
	else
		PORTA = (sinewave[pos1] + sinewave[pos2]) >> 1;	// averaging
}

//----------------------------------------------------------------
// main routine
// ---------------------------------------------------------------
int main()
{
	unsigned long freq1, freq2;	// DDS output frequency[Hz]
	unsigned char sw0_state, sw1_state, sw2_state;
	unsigned int tim;	
	unsigned char intflag;		// interrupt enable flag

	DDRA = 0b11111111;		// 8bit DDS output
	DDRB = 0b11111000;		// PB0,1,2 SW input
	PORTB = 0b00000111;		// pull up

	TCCR0A = 1;				// CTC0 enable
	TCCR0B = 0b00000001;	// Timer0 prescaler 1/1
	TIMSK = _BV(OCIE0A);	// Timer0 compare match A interrupt Enabled
	OCR0A = 199;			// clock 20MHz sampling 100kHz 20000000/160000=200(-1) = 199  
	
	sw0_state = sw1_state = sw2_state = 0;
	tim = 0;
	intflag = 0;
	phe1 = phe2 = 0;
	freq1 = DEF_LOW;		// default upside frequency
	freq2 = DEF_HIGH;		// default downside frequency
	
	sei();
	intflag = 1;
	sbi(PORTB, PB3);
	
	while(1) {
		delta1 = freq1 * ACCU / SF;
		delta2 = freq2 * ACCU / SF;

		// Low frequency increment
		if(bit_is_clear(PINB, PB1)) {
			sw0_state = 1;			
			delay_ms(10);
		}
		if(sw0_state && bit_is_set(PINB, PB1)) {
			sw0_state = 0;
			freq2 += FREQ_STEP;
			if(freq2 > MAX)
				freq2 = MIN;
		}
		// High frequency increment
		if(bit_is_clear(PINB, PB2)) {
			sw1_state = 1;
			delay_ms(10);
		}
		if(sw1_state && bit_is_set(PINB, PB2)) {
			sw1_state = 0;
			freq1 += FREQ_STEP;
			if(freq1 > MAX)
				freq1 = MIN;
		}
		// signal on/off
		if(bit_is_clear(PINB, PB0)) {
			sw2_state = 1;			
			delay_ms(10);
			tim++;
		}
		if(sw2_state && bit_is_set(PINB, PB0)) {
			sw2_state = 0;
			tim = 0;
			if(intflag) {
				cli();
				intflag = 0;
				cbi(PORTB, PB3);
			} else {
				sei();
				intflag = 1;
				sbi(PORTB, PB3);
			}			
		}
		// reset frequency (low 700Hz, high 2100Hz)
		if(tim > 100) {
			sw2_state = 0;
			tim = 0;
			freq1 = DEF_LOW;
			freq2 = DEF_HIGH;
		}
	}
}